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SY87700/701
Micrel
What Layout Tips Do You Have?
1. Establish controlled impedance stripline, microstrip,
or co-planar construction techniques for high-speed
signal paths.
2. All differential paths are critical timing paths, and
skew should be matched to within ± 10psec.
3. Signal trace impedance should not vary more than
± 5%. If in doubt, perform TDR analysis of signal
traces.
4. Maintain compact filter networks as close to filter
pins as possible.
5. Provide ground plane relief under the filter path to
reduce stray capacitance and be careful of crosstalk
coupling into the filter network.
6. Maintain low jitter on the REFCLK input by isolating
the XTAL oscillator from power supply noise by
adequately decoupling.
7. Keep the XTAL oscillator close to SY87700/701.
8. High speed operation may require use of
fundamental-tone crystal-based oscillator for
optimum performance. (Third overtone oscillators
typically have more jitter.)
9. Isolate the input, output, and REFCLK signal traces
from other clock and data signals on your board if
these other traces are within 3x the trace width.
Isolation can be achieved by putting ground traces
in between.
Should I Adjust the Loop Lilter?
The values found in the data sheets are the result of
extensive modeling as well as lab testing. Therefore, we
recommend starting with those values. Selecting values to
simply reduce jitter does not work since there is a trade-off
in jitter generation and jitter tolerance. However, for telecom
applications under Bellcore,ITU/CCIT specifications it may
be advantageous to adjust the values to trade off jitter
transfer for jitter generation.
4
Evaluation Board
How Do You Suggest We Qualify and Evaluate
Performance?
Evaluation should start by measuring the jitter of the
REFCLK input. The Clock Multiplier Unit (CMU) is simply a
PLL. It multiplies the incoming REFCLK frequency, and jitter
will usually worsen. The HP8133A pulse generator is ideal,
and the user should include a Transition Time Converter on
the 8133s output to slow its edges down. Make sure the
rise/fall times are reasonable (not 28ps rise/fall found on
the 12Gbps HP BERT clocks!) and 150ps TTCs will ensure
this. Measure the TCLK output jitter using either the ± side,
with the other side terminated. Suitable instruments for
measuring the TCLK jitter are the CSA803, 11801, or the
Wavecrest 2077. See Figure 1 for descriptions of set-up.
Characterization of the jitter must include accumulation of
many cycles or periods down to a specified low pass corner
frequency. Wavecrest makes this easy with their 6.1 version
software since the user can specify a low pass corner for
the collected jitter. The Wavecrest instrument cannot be set
up for single period measurements, but must look at the
difference between the rising edges of the REFCLK and
the TCLK using both channels and performing a histogram
of the propagation time between the input REFCLK (which
is the HP8133A trigger divided by one) and the output TCLK.
Evaluation of the CDR is similar, except that the RCLK
and RDOUT outputs are used instead. The procedure for
measuring the RCLK jitter is identical to the above procedure
for TCLK jitter.
Evaluation of the output jitter on RDOUT using RCLK as
a trigger source isn ’ t trivial, as the minimum time between
the scope trigger and measurement is 24ns for the Agilent
86100A scope. Therefore the user must delay the data by
the same amount, so that the jitter on RDOUT is measured
with respect to the correct clock edge. This is important, as
the SY87700/701 will retime the edges on RDOUT so that
they better align with RCLK. The Wavecrest DTS2077 can
also be used.
The setup for SONET jitter compliance tests is shown in
Figure 1. Agilent provides software for automated Bellcore
jitter compliance tests. Contact Agilent for details.
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